Level shift circuits (also referred to herein as level shifters) change the voltage level of a signal. For example, when an output voltage of a first circuit differs from an operating range of a second circuit, a level shifter is arranged between the first circuit and the second circuit, and the voltage level of the signal between the first and second circuits is adjusted. For example, in the driving circuitry for a liquid crystal display (LCD) panel, such as those using thin film transistors (TFT), signals having various voltages may be employed. In this case, signals having different voltages are generated from a common power supply, and one or more level shift circuits are provided to adjust the levels of the signals between circuit blocks having different voltages.
FIG. 1A illustrates a schematic diagram of a conventional level shift circuit 100. Conventional level shift circuit 100 includes transistors 110, 120, 130, inverter 105, and resistor 135. Transistor 110 and transistor 120 are operably coupled such that the drains of the two transistors 110, 120 are operably coupled. The source of transistor 120 is operably coupled with a relatively low voltage (VLOW), which may be, for example, ground. The source of the transistor 110 is operably coupled with the supply voltage (VHIGH). Transistor 130 is operably coupled in series with a resistor 135, such that the drain of the transistor 130 is coupled with an end of the resistor 135. The other end of the resistor 135 is operably coupled with VHIGH. The source of transistor 130 is operably coupled with VLOW. The gate of the transistor 110 is operably coupled with the node between the resistor 135 and the drain of the transistor 130. Level shifter 100 also includes an inverter 105 operably coupled with the gate of transistor 120.
An input signal (VIN) may be applied to level shifter 100 at the gate of transistor 130. VIN may also be applied to the inverter 105, such that the voltage signal applied to the gate of transistor 120 is the inverted signal of VIN. In operation, if VIN is asserted (i.e., has a high voltage relative to VLOW), transistor 130 is activated, which causes the voltage applied to the gate of transistor 110 to be approximately equal to VLOW. As a result, transistor 110 is also activated and VOUT is approximately equal to VHIGH. On the other hand, if V1 is not asserted (i.e., has a voltage near VLOW), transistor 130 is deactivated, which causes a high voltage applied to the gate of transistor 110. As a result, transistor 110 is deactivated. With VIN not asserted, the voltage applied to the gate of transistor 120 through inverter 105 is asserted, which activates transistor 120 and causes VOUT to be approximately equal to VLOW.
FIG. 1B is an output waveform 150 illustrating the output signal VOUT being generated in response to the input signal VIN for the conventional level shift circuit 100 of FIG. 1A. As shown in FIG. 1B, at time t1, VIN transitions from high to low (i.e., asserted to deasserted). For example, VIN may be approximately equal to VDD and transition to VLOW (e.g., 0V) at time t1. As a result, VOUT transitions from VHIGH to VLOW at time t2. The difference between the time that VIN transitions (i.e., t1) and the time that VOUT transitions (i.e., t2) from a high voltage to a low voltage may be the output falling time delay.
At time t3, VIN transitions from low to high. As a result, VOUT transitions from VLOW to VHIGH between times t3 and t5. At time t4, VOUT crosses the voltage midpoint between VLOW and VHIGH, which midpoint is approximately (VHIGH+VLOW)/2. The difference between the time that VIN transitions (i.e., t3) and the time that VOUT transitions (i.e., t5) from a low voltage to a high voltage may be the output rising time delay. Output rising time delay may be determined from a different voltage level than time t5 when VOUT is approximately equal to VHIGH. For example, one measure of the output rising time delay may be considered when VOUT crosses the voltage midpoint between VLOW and VHIGH (i.e., at time t4).
As shown in FIG. 1B, the input signal VIN is shifted successfully from an asserted signal (VDD) with a lower voltage to an output signal (VOUT) with a higher voltage (VHIGH), and which VOUT may control or otherwise operate compatible high voltage circuit functions. As shown in FIG. 1B, VIN may have an input voltage swing ranging from VLOW to VDD. VOUT has a different voltage swing ranging from VLOW to VHIGH.
One problem with the conventional level shift circuit 100 is that the output rising time delay may be relatively long—especially when compared to the output falling time delay. A relatively long output rising time delay may constrain system clock speeds. For example, the output rising time delay of the conventional level shift circuit 100 in FIG. 1A may constrain an integrated circuit to operate at a relatively low maximum clock frequency (e.g., 100 MHz), when the other circuit elements of the integrated circuit may otherwise be able to operate at a relatively greater frequency (e.g., 1 GHz).
The output rising time delay of the conventional level shift circuit 100 may be decreased by decreasing the resistance of the resistor 130. However, decreasing resistor 130 may also increase the standby current (ISB) that flows through the resistor 130 when the transition is complete (i.e., level shifter 100 is in a quiescent state) and VOUT is approximately equal to VHIGH. As a result, the power dissipated by the conventional level shifter 100 may increase during the quiescent state. The inventor has appreciated that there exists a need for a level shifter designed to reduce delays while maintaining relatively low shoot-through current and/or minimal standby current.